FORWARD DIFFERENCE EDGE DETECTOR BASED ON FPGA IMPLEMENTATION
DOI:
https://doi.org/10.11113/aej.v16.24274Keywords:
Edge Detection, FPGA, low power design, vhdlAbstract
This paper aims to develop and implement the forward difference edge detector on different Field Programmable Gate Array (FPGA) technologies. It investigates how different CMOS technologies influence the power dissipated by digital design. Digital design in terms of low power has become a very challenging problem. Recently, FPGAs, which are semiconductor devices, have been targeted for image processing applications to reduce the computational times needed due to their parallelism techniques. The forward difference algorithm is developed at a high level of abstraction and is performed using physical instruments to obtain real data that is valuable and essential. ModelSim Altera and Quartus Intel are used to describe the algorithm, selecting the VHDL language. The digital design for the forward difference edge detector is completely implemented and verified on Cyclone IV, Cyclone V, and Cyclone LP 10 FPGA devices. At the hardware level, more information is obtainable to estimate the power dissipation correctly. The results indicate CMOS technologies used can be determined based on the design specifications and their power dissipation.
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