SUB-0.4 W FULL-HD DARK CHANNEL PRIOR DEHAZING AT ~3.7 FPS ON EDGE DEVICES VIA AN HLS-BASED HARDWARE ACCELERATOR
DOI:
https://doi.org/10.11113/aej.v16.25026Keywords:
Hardware-accelerated system, Dark Channel Prior (DCP), Real-time Defogging, Peak Signal-to-Noise Ratio, High-level synthesisAbstract
Fast single-image dehazing is essential for safety-critical, vision-driven edge systems, but common algorithms such as Dark Channel Prior (DCP) are often too compute-heavy for low-power platforms. This study presents a complete, sub-0.4 W FPGA accelerator for full-HD (1920×1080) DCP dehazing on the low-cost PYNQ-Z2. Built with Vitis HLS and Vivado, the design partitions the pipeline into five streaming hardware kernels—minimum-channel extraction, dark-channel filtering, diffusion-map generation, radiance recovery, and LUT-based tone mapping—coordinated by the on-board ARM cores via AXI4 interconnects. To improve restoration quality without inflating hardware cost, this study further introduces a spatially varying atmospheric-light map derived from an anisotropic diffusion matrix and implement it in fixed-point arithmetic. Operating at 100 MHz, the accelerator processes 1080p images in 0.27 s (≈3.7 fps), providing about a 10× speedup over an ARM-only implementation while consuming 27.6k LUTs and 55 DSPs. Image-quality evaluation reports 22.48 dB PSNR, 0.93 SSIM, and the best BRISQUE score (20.16) among the compared methods. Compared with prior ASIC designs and higher-end FPGA implementations, the proposed solution offers a stronger cost–throughput–resource balance, demonstrating the practicality of HLS-based FPGA acceleration for real-time edge dehazing under tight power budgets.
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