FPGA-BASED MULTILAYER PERCEPTRON FOR FAST HUMAN ACTIVITY DETECTION

Authors

  • M Mohammed Sabir Hussain Department of Electronics & Communication Engineering, Muffakham Jah College of Engineering & Technology, India.
  • M A Raheem Department of Electronics & Communication Engineering, Muffakham Jah College of Engineering & Technology, India.
  • Taha Mazher Department of Electronics & Communication Engineering, Muffakham Jah College of Engineering & Technology, India.
  • Hakeem Ajaz Aslam Department of Electronics & Communication Engineering, Muffakham Jah College of Engineering & Technology, India.
  • K Sasidhar Department of Electronics & Communication Engineering, Muffakham Jah College of Engineering & Technology, India.
  • Afaq Ahmed Modern College of Business and Sciences, Bawshar St, Muscat 133, Oman

DOI:

https://doi.org/10.11113/aej.v16.25257

Keywords:

FPGA, Human Activity Recognition (HAR), Multi-Layer Perceptron (MLP), PLAN Activation, UCI HAR Dataset, Embedded Systems, Real-time Processing., FPGA

Abstract

This research presents an efficient Field-Programmable Gate Array (FPGA) implementation of a 7-6-5 Multi-Layer Perceptron (MLP) neural network for human activity recognition (HAR) using the UCI HAR dataset. The study addresses the growing need for low-power, real-time activity recognition systems suitable for embedded and wearable applications. A novel ReLU6 activation function is adopted to optimize the neural network for hardware deployment. The system processes seven selected features from accelerometer and gyroscope data to classify five activity classes: Walking, Sitting, Standing, Laying, and Activity Transitions. The design targets the Xilinx Artix-7 35T FPGA and includes complete Verilog hardware generation, encompassing network parameters, RELU6 activation lookup tables, and testbench validation. Quantitative results show high classification accuracy: 94.4% on Dataset A, 94.7% on Dataset B, and 94.1% on Dataset C, demonstrating consistent performance across different data splits. The results confirm that the proposed FPGA-based MLP offers a complete, real-time, hardware-ready solution for human activity recognition.

References

Zhang, X., Z. Luo, and Y. Wang. 2022. Comparative Analysis of Low‑Power Neural Network Accelerators. IEEE Access. 10:7549–7562.

DOI: https://doi.org/10.1109/ACCESS.2022.3142877

Lee, H., and H. Kim. 2022. Energy‑Efficient HAR Using Neural Networks on FPGAs. IEEE Transactions on Industrial Electronics.

DOI: https://doi.org/10.1109/TIE.2022.3161934

Islam, A., T. Islam, and F. Zulkernine. 2020. HAR Using Multimodal Sensor Fusion. IEEE Access. 8:176560–176574. DOI: https://doi.org/10.1109/ACCESS.2020.3026176

Xu, Y., H. Zhang, Y. Zhao, and F. Zhang. 2021. Improving Accuracy in HAR through Feature Optimization. Sensors. 21(9):2962. DOI:https://doi.org/10.3390/s21092962

Mahmoud, M., M. Shehata, A. Mokhtar, and A. Ahmed. 2021. Hardware‑Friendly Activation Functions for Deep Neural Networks. IEEE Access. 9:105158–105168.

DOI: https://doi.org/10.1109/ACCESS.2021.3100272Guan, Y., Y. [6] Guo, and D. Xu. 2020. A Lightweight HAR Model for Embedded Platforms. Sensors. 20(7):1925.

DOI: https://doi.org/10.3390/s20071925

Zhang, Y., and Q. Yang. 2015. Cross‑validation for Model Selection in HAR Tasks. IEEE Transactions on Pattern Analysis and Machine Intelligence. 37(9):1792–1804.

DOI: https://doi.org/10.1109/TPAMI.2014.2377715

Anguita, D., A. Ghio, L. Oneto, X. Parra, and J.L. Reyes-Ortiz. 2013. A Public Domain Dataset for HAR Using Smartphones. ESANN. 437–442.

DOI: https://doi.org/10.48550/arXiv.1312.5602

Palumbo, F., et al. 2017. Embedded HAR Through On-Chip Feature Extraction and Classification. Sensors. 17(3):485. DOI: https://doi.org/10.3390/s17030485

Han, S., H. Mao, and W.J. Dally. 2016. Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding. ICLR.

DOI: https://doi.org/10.48550/arXiv.1510.00149

Lara, O.D., and M.A. Labrador. 2013. A Survey on HAR Using Wearable Sensors. IEEE Communications Surveys & Tutorials. 15(3):1192–1209.

DOI: https://doi.org/10.1109/SURV.2012.110112.00192

Wang, J., Y. Chen, S. Hao, X. Peng, and L. Hu. 2019. Deep Learning for Sensor-Based HAR: A Survey. Pattern Recognition Letters. 119:3–11.

DOI: https://doi.org/10.1016/j.patrec.2018.02.010

Moons, B., B. De Brabandere, L. Van Gool, and M. Verhelst. 2017. Energy‑Efficient ConvNets through Approximate Computing. IEEE WACV.

DOI: https://doi.org/10.1109/WACV.2017.60

Qolomany, B., H. Al-Fuqaha, M. Guizani, A. Rayes, and M. Aloqaily. 2019. Parameter Optimization in ML: A Survey. Journal of Supercomputing. 75(9):1–45.

DOI: https://doi.org/10.1007/s11227-019-02935-4

Redmon, J., and A. Farhadi. 2018. YOLOv3: An Incremental Improvement. arXiv.

DOI: https://doi.org/10.48550/arXiv.1804.02767

Reuther, A., P. Michaleas, S.P. Bliss, J. Kepner, and W.M. Arcand. 2018. Survey & Benchmarking of ML Accelerators. IEEE HPEC.

DOI: https://doi.org/10.1109/HPEC.2018.8547536

Chen, Y., Y. Zheng, J. Liu, and B. Zhu. 2012. Noise‑Aware and Low‑Energy Activity Recognition Using Smartphones. ACM UbiComp.

DOI: https://doi.org/10.1145/2370216.2370260

Sze, V., Y.H. Chen, T.J. Yang, and J.S. Emer. 2017. Efficient Processing of Deep Neural Networks: A Tutorial. Proceedings of the IEEE. 105(12):2295–2329.

DOI:https://doi.org/10.1109/JPROC.2017.2761740

Venieris, S.I., and C.S. Bouganis. 2016. fpgaConvNet: A Toolflow for FPGA CNN Mapping. IEEE FPL.

DOI: https://doi.org/10.1109/FPL.2016.7577354

Zhang, C., P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong. 2015. Optimizing FPGA‑Based Accelerator Design for CNNs. ACM FPGA.

DOI: https://doi.org/10.1145/2684746.2689060

Bhattacharya, S., and N. Lane. 2016. Sparsification and Separation of Deep Learning for HAR. ACM MobiSys.

DOI: https://doi.org/10.1145/2906388.2906400

Yao, S., Y. Zhao, H. Shao, A. Zhang, and T. Abdelzaher. 2017. DeepSense: HAR on Mobile Devices Using Deep Learning. ACM SenSys.

DOI: https://doi.org/10.1145/3131672.3131673

Krishnan, N.C., and D. Cook. 2014. Activity Recognition on Streaming Sensor Data. Pervasive and Mobile Computing. 10:138–154.

DOI: https://doi.org/10.1016/j.pmcj.2012.07.003

Japkowicz, N., and S. Stephen. 2002. The Class Imbalance Problem: A Systematic Study. Intelligent Data Analysis. 6(5):429–449.

DOI: https://doi.org/10.3233/IDA-2002-6504

Masters, D., and C. Luschi. 2018. Revisiting Small Batch Training for Deep Neural Networks. arXiv.

DOI: https://doi.org/10.48550/arXiv.1804.07612

Melis, G., C. Dyer, and P. Blunsom. 2018. On the State of Reproducibility in Deep Learning. arXiv.

DOI: https://doi.org/10.48550/arXiv.1803.02398

Prechelt, L. 1998. Early Stopping — But When? In Neural Networks: Tricks of the Trade. Springer. 55–69.

DOI: https://doi.org/10.1007/3-540-49430-8_3

Goodfellow, I., Y. Bengio, and A. Courville. 2016. Deep Learning. Cambridge, MA: MIT Press. Chapter 7.

Kuon, I., and J. Rose. 2007. Measuring the Gap Between FPGAs and ASICs. IEEE Transactions on CAD. 26(2):203–215.

DOI: https://doi.org/10.1109/TCAD.2006.884574

Gaikwad, N. B., Tiwari, V., Keskar, A., & Shivaprakash, N. C. 2019. Efficient FPGA Implementation of Multilayer Perceptron for Real-Time Human Activity Classification. IEEE Access.

DOI: https://doi.org/10.1109/ACCESS.2019.2900084

Downloads

Published

2026-05-31

Issue

Vol. 16 No. 2: June 2026

Section

Articles