The Design Of Digital Test Simulator

Abstract

Digital Test Simulator is a Computer Aided Design (CAD) tools written in Turbo Pascal language ver. 5.0. It is a gate level simulator to measures the testability values of a combinational logic circuit. It was developed based on the testability analysis system called Computer-Aided MEsurefor LOgic Testability (CAMELOT). The measurement of the testability, controllability and observability for every nodes are based on the topologyical description of the circuit. The final results produced by simulator can be expressed in the form of table and histogram. Comparison of the various nodal testability values allows the areas of poor testability to be readily identified and the inprovement can be done to the circuits to make it more testable. Key Words: Logic circuit; Computer-Aided Design; CAMELOT approach; Digital Test Simulator