FPGA IMPLEMENTATION OF CNN FOR DEFECT CLASSIFICATION ON CMP RING

Authors

  • Ng Wai Kin School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 14300, Nibong Tebal, Penang, Malaysia
  • Mohd Shahrimie Mohd Asaari School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 14300, Nibong Tebal, Penang, Malaysia https://orcid.org/0000-0002-0225-4819
  • Bakhtiar Affendi Rosdi School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 14300, Nibong Tebal, Penang, Malaysi
  • Muhammad Firdaus Akbar School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 14300, Nibong Tebal, Penang, Malaysia

DOI:

https://doi.org/10.11113/jurnalteknologi.v83.16967

Keywords:

Convolutional Neural Network, Deep learning, Field Programmable Gate Array, Defect Classification, Automatic visual inspection

Abstract

Defect inspection is a crucial part of industrial manufacturing. However, it relies heavily on human effort on manual visual inspection. Various machine vision techniques have been introduced to replace human labour and to improve inspection quality and efficiency. The limitation of these techniques is that the algorithms need to be engineered again with each different use case. In this work, a Convolutional Neural Network (CNN) is used to classify the defects of the Chemical Mechanical Planarization (CMP) ring. The trained CNN model achieved an accuracy of 91% and the time taken for each inference process is around 1800 msec. To achieve computational efficiency, the CNN model is performed on the embedded device. The previous implementation of embedded CNN deploys OpenCL-based high-level synthesis accelerator on a high-end Field Programmable Gate Array (FPGA) board. In this work, the model inference is accelerated by PipeCNN FPGA implementation on Cyclone-VSE DE1-SoC, a low-end embedded FPGA board. Several configurations of hardware parameters are tested to search for the best setup of the FPGA resources. The hardware implementation has improved approximately seven times faster, as the inference time for each classification has improved from 1800 msec to 250 msec. However, the model implemented using the hardware is observed to produce lower inference accuracy as the accuracy drops from 91% to 81%.

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Published

2021-08-09

How to Cite

Wai Kin, N. ., Mohd Asaari, M. S. ., Rosdi, B. A. ., & Akbar , M. F. . (2021). FPGA IMPLEMENTATION OF CNN FOR DEFECT CLASSIFICATION ON CMP RING. Jurnal Teknologi, 83(5), 101-108. https://doi.org/10.11113/jurnalteknologi.v83.16967

Issue

Section

Science and Engineering