Optimisation of Process Parameters for Lower Leakage Current in 22 nm n-type MOSFET Device using Taguchi Method
DOI:
https://doi.org/10.11113/jt.v68.2994Keywords:
Taguchi Method, 22 nm n-type MOSFETs, high-k/metal gate, leakage current, Silvaco softwareAbstract
In this article, Taguchi orthogonal array method was used to optimize the process parameters during the design of a 22 nm n-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in order to decrease the leakage current (ILEAK) of the device. Titanium dioxide (TiO2) was used as the dielectric layer to replace the traditional silicon dioxide SiO2 and tungsten silicide (WSix) was used as a metal gate to replace polysilicon. The device’s fabrication and electrical characterization were executed using ATHENA and ATLAS modules from Silvaco International. Taguchi’s Power of Three Series L9 orthogonal array was used to optimize the device process parameters and to finally predict the best process parameter combination to obtain the minimum leakage current (ILEAK) using Smaller-the-Better (STB) signal-to-noise ratio (SNR). The optimization resulted in the attainment of the lowest ILEAK mean value of 0.25759 nA/µm which is in accordance to the predicted value given in the International Technology Roadmap for Semiconductors (ITRS) 2011.
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