ANALYSIS OF POWER CONSUMPTION SAR-ADC DYNAMIC COMPARATOR
DOI:
https://doi.org/10.11113/jt.v78.8779Keywords:
SAR-ADC, dynamic comparator, double tail dynamic comparator.Abstract
Due to the high demand of ultra-low power in digital application, the needs of energy efficient analog-to-digital converter (ADC) are really essential. The comparator being an important part of successive approximation register (SAR)-ADC needs to have optimum performance under low power condition. This paper presents the comparison on power consumption together with the output performance flow power SAR-ADC dynamic comparators from three different design proposed by previous researchers. The three circuits is simulated and compared in terms of power consumption, regeneration time, reset time and output transient. The simulation is using Cadence Spectre and setup with 0.18µm CMOS technology, VDD at 0.8V and clock speed 2 at MHz. The analysis results obtained provides the lowest voltage input different (ΔVin) possible for double tail dynamic comparator using 0.18µm CMOS technology while adhering to the 45 corner process requirement. The results can be used as references for further design of ultra-low power dynamic comparator.
References
Babayan S. and LotfiR. 2014. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator. IEEE Trans. On VLSI System. 22(2): 343-352
PaikD.,Miyahara M. and Matsuzawa A. 2011. An Analysis on a Pseudo-Diffrential Dynamic Comparator with Load Capacitance CalibrationinASIC (ASICON), IEEE 9th International Conference. 461 - 464.
Shinkel D.,KensinkE.,KlumperinkE., Van Tuijl E., and NautB.2007. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time, in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers. 314-415.
Goll B. and ZimmermannH.2009. A comparator with reduced delay time in 65-nm CMOS for supply voltage down to 0.65.IEEE Trans. Circuits Sys. II, Exp. Brief. 56(11): 810-814.
Elzakker M., Tuijil E., Geraedts P., SchinkelD., Klumperink E.A.M. and NautaB., 2010. A 10-bit Charge-Redistribution ADC Consuming 1.9uW at 1 MS/s. IEEE Jounal of Solid-State Circuits. 45: 1007-1015.
Brenna S., and Bonfanti A.2014. A 6-fJ/conversion-step 200-kSps asynchronous SAR ADC with attenuation capacitor in 130nm CMOS. i Analog Integr Circ Sig. Process. 81: 181-194
Downloads
Published
Issue
Section
License
Copyright of articles that appear in Jurnal Teknologi belongs exclusively to Penerbit Universiti Teknologi Malaysia (Penerbit UTM Press). This copyright covers the rights to reproduce the article, including reprints, electronic reproductions, or any other reproductions of similar nature.
