NEW ARCHITECTURE OF LOW AREA AES S-BOX/ INV S-BOX USING VLSI IMPLEMENTATION
DOI:
https://doi.org/10.11113/jt.v78.8782Keywords:
AES, S-box/ InvS-box, VLSI, low areaAbstract
The Substitution box (S-box) is one of the core of Advanced Encryption System (AES) implementation and the only non-linear transformation. It is consumed most of the power in AES hardware. This paper present a low-complexity design methodology for the S-box/ InvS-box which includes minimising the comprehensive circuit size and critical path delay, scaling down the transistor size, along with selecting an advanced technology for an optimised CMOS full custom design. The area of the circuit is about 39.44 µm2, while the hardware cost of the S-box/InvS-box is about 147 logic gates, with a critical path propagation delay of 3.235ns.
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