PERFORMANCE ANALYSIS OF INDUCTIVELY DEGENERATED CMOS LNA
DOI:
https://doi.org/10.11113/jt.v78.8938Keywords:
LNA, CMOS, inductive source degeneratedAbstract
This paper features the design approach of a low noise amplifier (LNA) which dissipates 19.89 mW from a 1.2 V power supply that was designed based on a 0.13 μm RFCMOS process. A detailed methodology that leads to a power-efficient design of the LNA is presented. A theoretical noise figure optimization using fixed power and physics-based gm/ID characteristics were used as a design optimization guide. Simultaneous noise and input matching under constrained power (PCSNIM) was achieved with an extra gate-source capacitor while gain enhancement was obtained by employing a capacitive feedback at the cascode transistor. The LNA is further optimized by implementing the forward biasing scheme to attain good LNA performance at low power. The end-design of the optimized LNA produces a noise figure of 3.55 dB, a power gain of 17.12 dB, a Third Order Input Intercept Point (IIP3) of -19.70 dBm, an input reflection coefficient of -14.15 dB and an output reflection coefficient of -18.37 dB. Simulated results validate peak performance at 2.45GHz, which makes the LNA suitable for Bluetooth and the industrial, scientific and medical (ISM) applications.
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