PACKAGE-ON-PACKAGE (POP) UNDERFILL PROCESS USING A MATERIAL DAM METHOD
Keywords:Package-on-Package, Underfill Process, L path-dispensing method, Material dam method, ball grid array
AbstractRecent developments in the electronics industry have introduced a multi-stack ball grid array (BGA) to meet the growing consumer demand for both high-performance and smaller-sized chip packages. This study focused on the preliminary study of the Package-on-Package (PoP) underfill process using a material dam method. High viscosity type of underfill material is considered for the underfill process. In the current experimental work, L path-dispensing method was chosen due to its advantages, as reported in the previous work. The material dam method was used to prevent underfill from moving backwards and flowing out from the dispensing region. The material dam was built surrounding the PoP package. The effectiveness of the underfill process was analyzed based on the cycle time and lateral lapping, which are significant factors in material selection. The experimental results revealed that slow underfill flow may cause the quickly harden of material while the dispensing process is still running. This situation restricts the underfill flow and creates voids in the PoP package. The material dam method successfully enhanced the underfilling process for layers 3 and 4 stacked-package. This study is expected to provide the preliminary underfill process of stacking the PoP package and is useful as a reference for the engineer in the microelectronics industry.
Vianco, P. and Neilsen, M., 2021. Processing and Reliability of Solder Interconnections in Stacked Packaging. In 3D Microelectronic Packaging, 471-526. https://doi.org/10.1007/978-981-15-7090-2_16
Yoshida, A., Taniguchi, J., Murata, K., Kada, M., Yamamoto, Y., Takagi, Y., Notomi, T. and Fujita, A., 2006, May. A study on package stacking process for package-on-package (PoP). In 56th Electronic Components and Technology Conference 2006, 6.
Zhang, J. and Baldwin, D.F., 2003, May. High-speed SMT compatible dispenseless underfill process for CSP BGA flip chip assembly. In 53rd Electronic Components and Technology Conference, 2003. Proceedings, 870-874.
Toleno, B.J. and Schneider, J., 2003, July. Processing and reliability of corner bonded CSPs. In IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. 299-304.
Ng, F.C., Abas, A., Ishak, M.H.H., Abdullah, M.Z. and Aziz, A., 2016. Effect of thermocapillary action in the underfill encapsulation of multi-stack ball grid array. Microelectronics Reliability, 66: 143-160.
Ong, E.E., Abdullah, M.Z., Khor, C.Y., Loh, W.K., Ooi, C.K. and Chan, R., 2012. Analysis of encapsulation process in 3D stacked chips with different microbump array. International Communications In Heat And Mass Transfer, 39(10): 1616-1623. https://doi.org/10.1016/j.icheatmasstransfer.2012.10.007
Khor, C.Y., Abdullah, M.Z., Tan, H.T., Leong, W.C. and Ramdan, D., 2012. Investigation of the fluid/structure interaction phenomenon in IC packaging. Microelectronics Reliability, 52(1): 241-252. https://doi.org/10.1016/j.microrel.2011.09.013
Abas, A., Ishak, M.H.H., Abdullah, M.Z., Ani, F.C. and Khor, S.F., 2016. Lattice Boltzmann method study of bga bump arrangements on void formation. Microelectronics Reliability, 56: 170-181. https://doi.org/10.1016/j.microrel.2015.10.014
Abas, A., Haslinda, M.S., Ishak, M.H.H., Nurfatin, A.S., Abdullah, M.Z. and Ani, F.C., 2016. Effect of ILU dispensing types for different solder bump arrangements on CUF encapsulation process. Microelectronic Engineering, 163: 83-97. https://doi.org/10.1016/j.mee.2016.06.010
Khor, C.Y., Abdullah, M.Z., Lau, C.S. and Azid, I.A., 2014. Recent fluid-structure interaction modeling challenges in IC encapsulation-A review. Microelectronics Reliability, 54(8): 1511-1526. https://doi.org/10.1016/j.microrel.2014.03.012
Lee, M.S., Baick, I.H., Lee, M., Kim, B., Lee, M., Kang, H., Kim, J., Rhee, H. and Pae, S., 2019, October. PCB Strip Scale Numerical Study on Vacuum Molded Underfill Void Entrapment in FC-POP Devices. In 2019 IEEE International Integrated Reliability Workshop (IIRW), 1-5. https://doi.org/10.1109/IIRW47491.2019.8989917
Lee, M.S., Baick, I., Jeong, M.S., Kim, M., Kwon, S.H., Yeo, M.S., Rhee, H. and Pae, S., 2020. Parametric Study on the Void Risk in FC-POP Molded Underfill Process Using a Novel Porous Media, Two-Phase, Compressible Flow Simulation Method. IEEE Transactions on Device and Materials Reliability, 20(2): 286-292.https://doi.org/10.1109/TDMR.2020.2985209
Lujan, A.P., 2018, May. Comparison of Package-on-Package Technologies Utilizing Flip Chip and Fan-Out Wafer Level Packaging. In 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2089-2094. https://doi.org/10.1109/ECTC.2018.00313
Hsieh, M.C., Lin, S., Hsu, I., Chen, C.Y. and Cho, N., 2017, September. Fine pitch high bandwidth flip chip package-on-package development. In 2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition, 1-5. https://doi.org/10.23919/EMPC.2017.8346847
Gagnon, P., Fortin, C. and Weiss, T., 2019, May. Package-on-Package micro-BGA Microstructure Interaction With Bond and Assembly Parameter. In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 306-313). https://doi.org/10.1109/ECTC.2019.00053
Gwon, H.R., Lee, H.J., Kim, J.M., Shin, Y.E. and Lee, S.H., 2014. Dynamic behavior of capillary-driven encapsulation flow characteristics for different injection types in flip chip packaging. Journal of Mechanical Science and Technology, 28(1): 167-173. https://doi.org/10.1007/s12206-013-0950-9
Babiarz, A.J., Paradigm Shift in Applying Underfill. Asymtek, Carlsbad, CA.
Khor, C.Y., Abdullah, M.Z. and Ani, F.C., 2012. Underfill process for two parallel plates and flip chip packaging. International communications in heat and mass transfer, 39(8: 1205-1212. https://doi.org/10.1016/j.icheatmasstransfer.2012.07.006
Khor, C.Y., Abdullah, M.Z. and Abdul Mujeebu, M., 2012. Influence of gap height in flip chip underfill process with non-Newtonian flow between two parallel plates, Journal of Electronic Packaging. 134(1): 011003 (6 pages) DOI: https://doi.org/10.1115/1.4005914
Majid, M.F.M.A., Khor, C.Y., Abdullah, M.K., Abdullah, M.Z., Rahiman, W.Y., Jappar, A. and Aris, M.S., 2012, November. Three Dimensional Numerical Prediction of Epoxy flow during the underfill process in flip chip packaging. In 2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT), 1-6. https://doi.org/10.1109/IEMT.2012.6521810