MODIFIED MATRIX CODES FOR SHIELDING MEMORIES AGAINST ADJACENT ERRORS
DOI:
https://doi.org/10.11113/aej.v14.20428Keywords:
Bit Overhead, Code Rate, Code Efficiency, Hamming Code, Matrix CodesAbstract
Soft errors are caused in memories due to radiation effects as the technology scales down. This paper concentrates on correcting adjacent errors in memories using indirect decoding mechanisms. Several matrix codes were also used to correct a maximum of two adjacent and random errors. In this paper, matrix representation of two rows for half the data bits matrix representations is used and each row is encoded with extended hamming code parity bits. Three ways of decoding are proposed. Among them, the method-1 uses only extended hamming bits of rows and vertical parity bits for decoding which is capable of correcting odd number of adjacent bits in half of data bits. The method-2 uses all parity bits and is capable of correcting 1 bit less than half the data bits. The method-3 uses all parity bits and with a change in decoding mechanism allows correction of half erroneous data bits. The method-3 based decoder proves to be more reliable either in lower half or upper half of Data, enabling it to be used in image processing applications. But method-3 compromises with decrease in code rate, increase in bit overhead, area and power delay product by atleast 26.38%, 10.76%, 9.6% and 5%.
References
A. S.-Macián, P. Reviriego, J. A. Maestro. 2014. Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes Through Selective Shortening and Bit Placement. IEEE Transactions on Device and Materials Reliability, 14(1): 574-576, March. DOI: 10.1109/TDMR.2012.2204753.
S. Tambatkar, S. N. Menon, V. Sudarshan, M. Vinodhini, N. S. Murty. 2017. Error detection and correction in semiconductor memories using 3D parity check code with hamming code. 2017 International Conference on Communication and Signal Processing (ICCSP), 0974-0978. DOI: 10.1109/ICCSP.2017.8286516.
K. Neelima, C. Subhas. 2020. Efficient Adjacent 3D Parity Error Detection and Correction Codes for Embedded Memories. 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 1-5. DOI: 10.1109/CONECCT50063.2020.9198452.
S. Sharma, P. Vijayakumar. 2012. An HVD based error detection and correction of soft errors in semiconductor memories used for space applications. 2012 International Conference on Devices, Circuits and Systems (ICDCS), 563-567. DOI: 10.1109/ICDCSyst.2012.6188771.
V. Badole, A. Udawat. 2014. Implementation of multidirectional parity check code using hamming code for error detection and correction. International Journal of Research in Advent Technology, 2: 1-6. DOI: https://1library.net/document/zx25v8oq-implementation-multidirectional-parity-check-using-hamming-detection-correction.html.
M. S. Rahman, M. S. Sadi, S. Ahammed, J. Jurjens. 2015. Soft error tolerance using Horizontal-Vertical-Double-Bit Diagonal parity method. 2015 International Conference on Electrical Engineering and Information Communication Technology (ICEEICT), 1-6. DOI: 10.1109/ICEEICT.2015.7307411.
L. J. Saiz-Adalid, P. Gil, J. C. Ruiz, J. Gracia-Morán, D. Gil-Tomás, J.-C. Baraza-Calvo. 2016. Ultrafast Error Correction Codes for Double Error Detection/Correction. 2016 12th European Dependable Computing Conference (EDCC), 108-119. DOI: 10.1109/EDCC.2016.28.
K. Neelima, C. Subhas. 2019. Multiple Adjacent Bit Error Detection and Correction Codes for Reliable Memories: A Review. Conference Advances in Communications, Signal Processing, and VLSI. Lecture Notes in Electrical Engineering, 357-371. DOI: 10.1007/978-981-33-4058-9_32.
J. Athira, B. Yamuna. 2018. FPGA Implementation of an Area Efficient Matrix Code with Encoder Reuse Method. 2018 International Conference on Communication and Signal Processing (ICCSP), 0254-0257. DOI: 10.1109/ICCSP.2018.8524371.
A. J. Olazábal, J. P. Guerra. 2019. Multiple Cell Upsets Inside Aircrafts. New Fault-Tolerant Architecture. IEEE Transactions on Aerospace and Electronic Systems, 55(1): 332-342. DOI: 10.1109/TAES.2018.2852198.
J. Samanta, J. Bhaumik, S. Barman. 2019. Compact and power efficient SEC-DED codec for computer memory. Microsystem Technologies, 27: 359-368, Feb. DOI:10.1007/s00542-019-04366-7.
K. N. Dang, X. T. Tran. 2019. An Adaptive and High Coding Rate Soft Error Correction Method in Network-on-Chips. VNU Journal Of Science: Computer Science And Communication Engineering, 35(1): 32–45. DOI:10.25073/2588-1086/vnucsce.218.
A. Radonjic, V. Vujicic. 2019. Integer codes correcting sparse byte errors. Cryptography and Communications, 11(5): 1069-1077, Sep. DOI: 10.1007/s12095-019-0350-9.
A. Subbiah, T. Ogunfunmi. 2019. A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs). Micromachines, 10(6): 1-15. May. DOI: 10.3390/mi10060365.
S. Lin, K. A. Ghaffar, J. Li, K. Liu. 2020. A Scheme for Collective Encoding and Iterative Soft-Decision Decoding of Cyclic Codes of Prime Lengths: Applications to Reed–Solomon, BCH, and Quadratic Residue Codes. IEEE Transactions on Information Theory, 66(9): 5358-5378. DOI: 10.1109/TIT.2020.2978383.
U. S. Himaja, M. Vinodhini, N. S. Murty. 2018. Multi-Bit Low Redundancy Error control with Parity Sharing for NoC Interconnects. 2018 3rd International Conference on Communication and Electronics Systems (ICCES), 61-65. DOI: 10.1109/CESYS.2018.8724118.
A. Das, N. A. Touba. 2018. Low complexity burst error correcting codes to correct MBUs in SRAMs. Proceedings of the 2018 on Great Lakes Symposium on VLSI, 219-224. DOI: 10.1145/3194554.3194570.
S. Divya Lakshmi, K. Neelima, C. Subhas. 2021. Proficient Matrix Codes for NOC Applications. 2021 International Symposium on Devices, Circuits and Systems (ISDCS), 1-4. DOI: 10.1109/ISDCS52006.2021.9397914.
J. Guo, L. Xiao, Z. Mao, Q. Zhao. 2014. Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(1): 127-135, Jan. DOI: 10.1109/TVLSI.2013.2238565.
Neelima, K., Subhas, C. 2022. Half Diagonal Matrix Codes for Reliable Embedded Memories. International Journal of Health Sciences, 6(S2): 11664 – 11677. DOI: https://doi.org/10.53730/ijhs.v6nS2.8117
Ms. Gunduru Swathi Lakshmi, Ms. Neelima K, Dr. C. Subhas. 2019. Error Detection and Correction Methods for Memories used in System-on-Chip Designs. International Journal of Engineering and Advanced Technology (IJEAT), ISSN: 2249 – 8958, 8(2S2): 60-66. DOI: B10140182S219/19©BEIESP.
Nimisha N, P Rajkumar , S Rajkumar. 2020. Error Correction Codes using Burst and Random Errors for Multiple Cell Upsets in Space Application. International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering, 8(5): 30-45. May. DOI: 10.17148/IJIREEICE.2020.8507.
Neelima Koppala, Chennapalli Subhas. 2022. Low Overhead Optimal Parity Codes. Telkomnika (Telecommunication Computing Electronics and Control), 20(3): 501-509, ISSN: 1693-6930. DOI: 10.12928/TELKOMNIKA.v20i3.23301.
S. Manoj, C. Babu. 2016. Improved error detection and correction for memory reliability against multiple cell upsets using DMC & PMC. 2016 IEEE Annual India Conference (INDICON), 1-6. DOI: 10.1109/INDICON.2016.7839094.
Gobinda Prasad Acharya, Muddapu Asha Rani, Ganjikunta Ganesh Kumar, Lavanya Poluboina. 2022. Adaptation of March -SS Algorithm to word-oriented memory built-in self-test and repair. Indonesian Journal of Electrical Engineering and Computer Science, 26(1): 96-104. DOI: 10.11591/ijeecs.v26.i1.pp96-104.
Neelima K, C. Subhas, 2023. Modified Proficient Adjacent Error Correcting Codes. e-Prime - Advances in Electrical Engineering, Electronics and Energy, 5: 100277, ISSN 2772-6711, https://doi.org/10.1016/j.prime.2023.100277.
