QUAD FLAT NO-LEAD PACKAGE WITH DIFFERENT THERMAL PROFILES AND SOLDER PAD FINISHING FOR VOID MINIMIZATION

Abstract

Voiding in solder joints is a common problem that occur in electronic packaging, specifically for bottom terminated component (BTC). Quad Flat No-Lead (QFN) is a good example of BTC component that susceptible to void. Thus, QFN component thermal pads were used as the test vehicle in this voiding assessment. The objectives of this study are to analyze the influence of the variables from every parameter evaluated in the experiment on voiding area in QFN thermal pad solder joint and obtain the best combination of variables that can minimize the total void area percentage inside QFN thermal pad solder joint down to below 5%. In this study, several variables and their impacts on voiding based on the literature review were studied. No clean lead-free solder paste of SAC305 composition was employed in this experiment. Various stencil patterns were tested, including Window-Pane, Round, and Triangle/Polygon. The influence of pad surface finishing of the test board on the voiding reduction was analyzed in this study. The effects of convection reflow of various profiles and atmospheres were also considered. All the variables were setup for the experiment execution which begins by solder paste printing, solder paste inspection, component pick & place, convection reflow soldering, Xray inspection, void data extraction & analysis, and finally void results compilation. The results shown that reflow profile Ramp-To-Spike (RTS) Long Reflow Time High Peak Temperature gave lesser void area % than Ramp-Soak-Spike (RSS) Long Soak and RTS Normal profiles.