OPTIMIZATION OF PROCESS PARAMETERS FOR GOLD-DOPED SILICON IN RF APPLICATION
DOI:
https://doi.org/10.11113/jurnalteknologi.v87.23462Keywords:
High resistivity silicon, gold-doped silicon substrate, RF substrate, parasitic surface conduction (PSC)Abstract
Gold-doped high resistivity silicon has shown potential as advanced RF substrate through improved substrate resistivity and RF performances. However, the substrate demonstrates non-linear behavior, indicating insufficient traps to fully pin the Fermi level to intrinsic level. To date, charge-trapping mechanism of the substrate has not been fully understood. This study aims to highlight the effects of process variations in the development of gold-doped high resistivity silicon on the DC and RF performances to gain a deeper insight into the charge-trapping mechanism associated with the substrate. Double-stage activation annealing consists of controlled cooling and rapid cooling illustrates higher resistivity compared to single-stage annealing, with more than 50% increase. In addition to that, CPW losses demonstrate lower dependency on DC bias, reflected by its amax/amin ratio of 1.01 as compared to 1.24 for single-stage annealing. Through this work, it was also found that the substrate is sensitive to high-temperature processing, indicated by the higher amax/amin loss ratio on thermally oxidized substrate, most likely due to the insufficient traps to compensate for the additional thermal generated carriers. Additionally, the removal of gold layer at the silicon surface was unwarranted from the RF perspective, portrayed by the higher CPW losses.
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