DESIGN AND COMPARATIVE ANALYSIS OF FINFET BASED 6 T AND 7T-SRAM CELLS FOR IN-MEMORY COMPUTING APPLICATIONS
DOI:
https://doi.org/10.11113/aej.v15.23867Keywords:
Average power dissipation, static noise margin, FinFET, SRAM, Multi-Gate Transistors, Memory DensityAbstract
Since memories are the core components of most digital systems, lowering their power usage can significantly affect the system's stability, performance, and efficiency. SRAM cells are suitable for embedded and portable electronics due to their lower leakage. FinFETs have demonstrated their potential as a low-power, high-performance option at lower technological nodes. One of the main priorities for designers working on semiconductor memories is low power consumption, which can be achieved by reducing transistor leakage current. This article design and compares the average power consumption and noise voltage of 6T as well as 7T SRAM cells using FinFET approach for In-memory computing applications. It has been found that the stability and power handling capacity of an SRAM cell constructed using 45 nm FinFET technology are improved. The proposed 7T FinFET SRAM reduces average power dissipation by approximately 12% and increases the average noise voltage by approx. 7% as compared to 6T SRAM cells. Cadence Virtuoso ADE is used for all designs and simulations.
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